The present invention relates to a circuit substrate, a detector using the circuit substrate, and a method of manufacturing the same and, more particularly, to a circuit substrate having electrodes exposed also on the lower surface side of the substrate.
Assume that a technique of connecting the electrodes formed on a semiconductor substrate to an external device by using bonding wires is applied to a detector having a detecting section formed on a substrate surface to detect the flow rate and velocity of a fluid (e.g., Japanese Patent Publication No. 6-25684). In this case, the wires disturb the flow of a fluid, adversely affecting measurement. In addition, the wires hinder a plurality of semiconductor substrates from being stacked into one semiconductor device. Furthermore, since the electrode extraction portions are exposed on the substrate surface, the electrode portions may undergo electrolytic corrosion.
Conventionally, as techniques of connecting the electrodes formed on a semiconductor substrate to an external device without using any bonding wire, the following techniques are known:
{circle around (1)} lower-surface electrode extraction technique (Japanese Patent Laid-Open No. 7-14874);
{circle around (2)} lower-surface electrode extraction technique using anisotropic etching technique; and
{circle around (3)} electrode extraction technique using deep etching technique.
According to lower-surface electrode extraction technique (Japanese Patent Laid-Open No. 7-14874) {circle around (1)}, an electrode extraction structure is designed such that a through hole is formed in a semiconductor substrate, and a conductive layer (pad) connected to part of an internal circuit is formed in the hole to be exposed on the substrate surface. This hole is formed as follows. First, oxide films are formed on the upper and lower surfaces of the semiconductor substrate. Windows are then formed in the oxide films on the upper and lower surfaces. Silicon etching is performed from the upper and lower surface sides by using the oxide films as masks.
In the structure of such an electrode extraction portion, each pad portion is exposed on both the upper and lower surfaces of the substrate. For this reason, when a semiconductor chip is to be mounted by wire bonding, the upper surface side of each pad portion can be used as an electrode extraction portion. When this process is to be performed by a bump method, the lower surface side of each pad portion can be used as an electrode extraction portion.
In lower-surface electrode extraction technique {circle around (1)}, however, after a hole is formed, a metal is embedded in the hole to form a conductive layer. If this conductive layer is formed before other IC manufacturing processes, a high-temperature process cannot be performed because the metal of the conductive layer causes contamination.
Assume that the substrate is not an insulator. In this case, to form a hole in the substrate after an IC manufacturing process or the like, a conductive portion penetrating through the substrate must be isolated from the substrate itself by an insulator. If, for example, the substrate is made of silicon, the optimal insulator is a thermal oxide film. However, a high temperature is required for a growth process of this thermal oxide film. It is therefore difficult to form holes after the process of forming an IC or the like.
In general, the interconnections on a substrate are located on insulating films such as oxide and nitride films. To cause a conductive layer penetrating through the substrate to come into contact with the interconnections, these oxide films must be selectively etched through deep holes. In this case, if both the insulating film used to insulate the substrate from a conductive portion and the insulating film having interconnections formed thereon are oxide films, it is very difficult to selectively etch these insulating films.
According to the structure of a lower-surface electrode extraction portion based on technique using anisotropic etching {circle around (2)}, as shown in FIGS. 42A to 42D, since a semiconductor substrate 1 is etched by the anisotropic etching technique, the area of an electrode extraction portion 10 on the lower surface is several times larger than the contact area on the upper surface of the substrate. For this reason, when a small device or a device having many electrodes is to be manufactured, in particular, since the area of each electrode extraction portion on the lower surface becomes large, the device area becomes large. This technique is not therefore practical.
In addition, in the structure of this electrode extraction portion, a metallized layer 12 may be formed from the lower surface side while a membrane 11 is left on the upper surface. In this case, if a process on the upper surface side is performed after metallizing and soldering processes (or other processes such as a plating process), the problem of contamination in a heating process or the like is posed. If metallizing is performed in the last step in the manufacturing process, it is very difficult to keep the membrane 11 intact in the preceding steps in the process. For this reason, a general process cannot be used, and hence this technique cannot be used in practice. Reference numeral 13 denotes a solder; 14, a upper-surface electrode interconnection; and 15, a protective film.
According to the structure of an electrode extraction portion based on technique using deep etching {circle around (3)}, as shown in FIGS. 43A to 43D, since a hole 16 having a substantially constant diameter can be formed in a semiconductor substrate 1, the problem of a device size in anisotropic etching in FIG. 42D can be solved. However, the problems of contamination in a heating process and breakdown of a membrane 11 remain unsolved. In addition, this method must deal with the problem of how to form a contact window 17 in an insulating layer 3 without etching the wall of the hole. In general, a thermal oxide film 18 is an optimal film to be formed on the wall of a hole. However, the insulating layer 3 on the upper surface is often an oxide film. In this case, no problem is posed if the side surface of the hole can be covered with a resist in a photolithography process. It is, however, very difficult to apply photolithography to the almost vertical wall of the hole having such a large aspect ratio.
The present invention has been made to solve the above problems in the prior arts, and has its object to provide a circuit substrate and a detector in which electrodes are formed in the thickness direction of a substrate to allow connection of the electrodes from the lower surface side of the substrate while the problems of contamination, breakdown of membranes, and the like are solved altogether.
In order to achieve the above object, according to the present invention, there is provided a circuit substrate characterized by comprising an electrical insulating region which is formed on a semiconductor substrate, made of a heat-resistant insulating material, continuously extends from an upper surface to lower surface of the semiconductor substrate, and is closed in a plane parallel to the surface of the semiconductor substrate, wherein the electrical insulating region separates the semiconductor substrate into first and second electrically insulated/isolated regions, the first region is surrounded by the electrical insulating region, the second region is located outside the electrical insulating region, and the first region has a high impurity concentration to have conductivity.
In addition, according to the present invention, there is provided a circuit substrate characterized by comprising an electrical insulating region which is formed on a semiconductor substrate of the same conductivity type with different impurity concentrations in a thickness direction, made of a heat-resistant insulating material, continuously extends from an upper surface to lower surface of the semiconductor substrate, and is closed in a plane parallel to the surface of the semiconductor substrate, wherein the electrical insulating region separates the semiconductor substrate into first and second electrically insulated/isolated regions, the first region is surrounded by the electrical insulating region, the second region is located outside the electrical insulating region, and the first region has a high impurity concentration to have conductivity.
In addition, according to the present invention, there is provided a circuit substrate manufacturing method characterized by comprising the steps of: forming, on a semiconductor substrate, an electrical insulating region which is made of a heat-resistant insulating material, continuously extends from an upper surface to a lower surface of the semiconductor substrate, and is closed in a plane parallel to the surface of the semiconductor substrate, and separating the semiconductor substrate into first and second electrically insulated/isolated regions, the first region being surrounded by the electrical insulating region and the second region being outside the electrical insulating region; and diffusing an impurity into the first region, of the semiconductor substrate, which is surrounded by the electrical insulating region to make the first region have conductivity.
As has been described above, according to the present invention, since the inside of a substrate having conductivity is separated into electrically insulated/isolated regions by a heat-resistant insulating material, a conductive region surrounded by the electrical insulating region can be used as an electrode. This electrode can be extracted from the lower surface side. Therefore, no wire bonding is required.
Since each electrode is formed by impurity diffusion, no electrode material needs to be embedded in the substrate. In addition, the above electrode is formed before the formation of the membrane and the like. This solves the problems of contamination, breakdown of a membrane, and the like in the IC manufacturing process.
In addition, according to the present invention, since the electrical insulating regions are formed on the semiconductor substrate having different impurity concentration distributions in the thickness direction, a lower-surface extraction electrode can be formed by less impurity diffusion. Furthermore, an IC and the like can be formed on the side of the substrate which has a lower impurity concentration.